1. Field of the Invention
The present invention relates to a memory access system which allows a plurality of data processing units to write data in a single storage unit (memory) or read data therefrom, and a memory control apparatus, a memory control method, and a program which are adapted to the memory access system.
Particularly, the present invention relates to a memory access system which has a bus arbitrating unit which arbitrates contention of a bus in use at the time a plurality of data processing units connected to the bus write data in a single storage unit or read data therefrom, and a memory control apparatus which controls the storage unit, and a memory control apparatus, a memory control method, and a program which are adapted to the memory access system.
2. Description of the Related Art
A memory access system in which a plurality of data processing units perform data writing or data reading on a single storage unit (memory), e.g., a single DRAM is used in various fields.
There is a memory access system (or signal processing system) in which a plurality of data processing units write image data to a single memory and read written image data from the memory, so that the plurality of data processing units use the image data stored in the memory to execute desired signal processing.
In such a memory access system, there is a case where a plurality of data processing units simultaneously generate data write requests or data read requests with respect to a single memory.
Hereinafter, a data write request or a data read request with respect to a storage unit (memory) is generally termed as “access request” with respect to a storage unit (memory).
A bus arbitrating unit (bus arbiter) arbitrates contention of bus usage when access requests are generated from a plurality of data processing units with respect to a single memory at the same timing.
A memory such as DRAM can be accessed bank by bank.
In this respect, there is an attempt such that when a plurality of data processing units make access requests, a memory controller is provided between the bus and the memory to process the access requests bank by bank to enable bank-by-bank access, thus improving the memory access efficiency.
Related arts which improve such a memory access efficiency are exemplified below.
Patent Document 2 (JP-A-2007-18222) discloses a technique of dividing an access request from a data processing unit (bus master) to a memory bank by bank, and combines the access request with an access request from another data processing unit when there is a bank which does not involve a transfer request. This improves the memory access efficiency.
Patent Document 2 (JP-A-2006-260472) discloses a technique of changing the bank-by-bank order of access requests without particularly limiting the rearrangement of the access requests.
However, when the methods disclosed in Patent Documents 1 and 2 are used, the order of memory accesses from different bus masters (data processing units) is changed. The details are given later in comparison with embodiments of the present invention.
When the order of memory accesses from different bus masters (data processing units) is changed, there may be a case where even if a bus master B attempts to read data written by a bus master A immediately after the data is written, the bus master cannot read the data written by the bus master A. A specific example of the case is described later in comparison with the embodiments of the present invention referring to the accompanying drawings.